In many of today's microprocessor interfaces or other interfaces, a low frequency clock signal such as 250 MHz is required on initial boot-up of, for example, the central processing unit (CPU) or other circuit. However, after the CPU finishes initializing all required states, the microprocessor requires a clock signal at a higher frequency, such as 1 GHz, to run at full speed. Because many microprocessor interfaces require multiphase clock inputs, they may be generically labeled “interfaces requiring multiphase clocks.” A high speed point-to-point data transfer structure, such as HyperTransport® developed by a consortium of companies is an example of such an interface.
FIG. 1 shows a prior art configuration of a single multiphase clock generator 104 generating a plurality of multiphase output signals 120 from a reference clock signal 103. It is recognized that the words “signal” and “clock” as used throughout this disclosure shall include both digital and analog information provided by a particular source. The reference clock signal 103 may be provided by a reference clock source 102, such as a host processor, not shown, or other suitable clock source. As illustrated, the plurality of multiphase output signals 120 generated by the multiphase clock generator 104 are output to an interface requiring multiphase clocks 106. Generally, multiphase voltage controlled oscillator (VCO) clocks 122 are generated by a phase locked loop (PLL) 108 or other clock source buffered by each stage of a voltage controlled oscillator (VCO) 110. The multiphase VCO clocks 122 share a common frequency, but have different phases. As recognized, the number of stages within the VCO 110 will determine the phase difference between each signal among the multiphase VCO clocks 122. For example, a four stage differential VCO can produce four differential signals that are 45 degrees apart.
The reference clock signal 103 is fed into the phase frequency detector (PFD) 112. The PFD 112 compares the reference clock signal 103 to the feedback clock signal 115 as provided by feedback dividers 114. The PFD 112 then outputs an up or down voltage signal 113 to the charge pump/loop filter 116. The charge pump/loop filter 116 receives the voltage signal 113 and pumps up or down the current accordingly and translates it into a control voltage. Based upon the current and control voltage from the charge pump/loop filter 116, the VCO 110 can be sped up or slowed down accordingly. The output of the VCO 110, i.e., the multiphase VCO clocks 122, is then buffered by output clock buffers 118 prior to output as a plurality of multiphase output signals 120. At the same time, the multiphase VCO clocks 122 are feed back to the PFD 112 via the feedback dividers 114. As is recognized, the VCO 110 can be implemented either as a single-ended or differential VCO.
In order to produce multiphase VCO clocks 122 and, indirectly, the plurality of multiphase output signals 120, the PLL 108 must be in a locked state. A first prior art solution to providing pluralities of multiphase output signals at two or more frequencies is to implement the apparatus of FIG. 1, produce a plurality of multiphase output signals at a first frequency, relock the PLL, produce a plurality of multiphase output signals at a second frequency, and repeat if more frequencies are requested. A typical lock time of a PLL is at least 5 micro seconds (e.g., 5 us). However, many of today's interfaces requiring multiphase clocks 106 (such as the HyperTransport® microprocessor interface) require frequency transitions within an adjacent reference clock period (e.g., 1 us) for proper operation. Therefore, this first solution is inherently problematic. That is, a PLL 108 must be able to produce a plurality of multiphase output signals at a first frequency, relock at a second frequency and produce a plurality of multiphase output signals at a second frequency within a short amount of time for normal operation of the interface 106. As a result, a need exists to provide pluralities of multiphase output signals at different frequencies, i.e., multiphase clocks, in a short amount of time.
A second prior art solution that addresses the need to provide pluralities of multiphase output signals at different frequencies in a short amount of time is generally shown in FIG. 2. The solution requires two multiphase clock generators 104 and 202 each utilizing a PLL 108 to respectively generate a plurality of multiphase output signals at “A” MHz 120 and another plurality of multiphase output signals at “B” MHz 206. A selection stage, such as a multiplexer 204, is provided to receive both pluralities of multiphase outputs signals at “A” and “B” MHz 120 and 260 and selectively output desired signals 209 based upon a multiplexer control signal 208. While this solution is capable of, among other things, providing both pluralities of multiphase output signals 120 and 206 to an interface requiring multiphase clocks within an adjacent reference clock period, it is largely impractical. The power consumed and the area required within a computer system to implement two multiphase clock generators such as 104 and 202 can make this solution cost-ineffective.
A third prior art solution supplying discrete wide-range frequencies (i.e., a multiphase clock having a desired frequency and a desired difference) requires an oscillator, a first selecting means and a frequency dividing means. The oscillator generates a first multiphase clock having a predetermined frequency and having a number of clock signals each shifted in phase by a first phase difference value. The first selecting means receives the first multiphase clock and outputs a second multiphase clock including the same or a different number of clock signals each shifted in phase by a second phase difference value. The second phase difference is n times as long as the first phase difference, where n is an integer. Lastly, the frequency dividing means receives the second multiphase clock and divides the frequency of the second multiphase clock by a predetermined number and outputs a group of clock signals as a third multiphase clock. The third multiphase clock has a frequency determined by the frequency dividing means and a phase difference among the signals equal to that of the second multiphase clock output from the first selecting means.
This prior art solution can inherently suffer from additional serial or cascaded components during the clock output path. Among other things, this approach requires a first selection means to receive a first multiphase clock and output a second output clock having the same or different number of clock signals with a second phase difference prior to frequency division. As a result, the solution can suffer from unnecessary system components and potentially unwanted jitter.
Therefore, a need exists to generate multiphase output signals at different frequencies, i.e., multiphase clocks, in a short amount of time (e.g., within an adjacent reference clock period ) while keeping power consumption and circuit area to a minimum. A further need exists to generate multiphase output signals at different frequencies while reducing unnecessary circuit redundancy and jitter common in many multiphase clock generators and frequency dividers.